Amateur Radio Site Of  VE1XYL & VE1ALQ  

ChatRoom | GuestBook | Forum
32Bit Software | 16Bit Tracking | DOS Tracking |
DOS Tracking | RF Software | DOS EME Planner
Latest ref-Lock & VCXO | ref-Lock & JTAG | Early BCD PLL's | Visit Luis, CT1DMK |
subglobal4 link subglobal4 link
subglobal6 link subglobal6 link
New PLL System.

This page will be updated as Material becomes available. This New System will essentially replace the original BCD Design originally designed by WB6IGP and N6IZW and appeared in  ARRL UHF/Microwave Project Manual.  Their efforts were later revised by WA6CGR.

This New Design eliminates the many short Falls of the BCD Divider Chips and Implements actually 3 PLL Circuits that are extremely clean up to and including 47Ghz. One Huge advantage of this System is the ability to select any divisor factor appropriate for any XTAL Freq. i.e. 94.666667Mhz to sight one example only.

Please check Back Soon.

Below are some Image indicating what will follow as time permitts.

 

New PLL System. Schematic:

 

 

106Mhz VCXO for 24 & 47Ghz, installed in an Old Brick Housing:

 

 

Tri-PLL System, again installed in the seconds compartment of the same Brick Housing as VCXO Above. This is one extreemly clean system and sound like a pure XTAL Osc. at 24 & 47Ghz.

|Copy Write ©2003 ve1alq        Designed using Dreamweaver MX